Programmable logic arrays (PLAs) are used in many applications to realize logic functions involving a relatively large number of inputs and a relatively large number of outputs. The PLA is a matrix of row input lines which are selectively coupled to column output lines to form logical AND or logical OR functions, or combinations of logical AND and logical OR functions.
The major advantages of PLAs are that they are easily programmable and that they provide a highly dense layout of the logic functions on an integrated circuit chip. PLAs can also provide relatively low power logic, by using precharge signal to precharge the columns prior to enabling the row input signals. However, in prior art PLAs, once the columns have been precharged, the row inputs must be enabled and the column lines sampled relatively soon after the precharge is ended, or the precharge signal on the column lines may decay below the minimum voltage for a logical 1 level. For this reason, these PLAs are sometimes referred to as dynamic PLAs. However, there are conditions which call for high density, low power PLAs which also must operate in a static manner, since the time between the end of the precharge signal and the sampling period may vary widely.
Therefore, it can be appreciated that a circuit such as a high density pull-up circuit which enables a high density, low power PLA to operate as a static PLA is highly desirable.